1. Field of the Invention
The present invention relates to a DTV(Digital television), and more particularly to an apparatus and method for removing error data by decoding delay in a DTV capable of performing error data removal and sync signal delay resulting from the decoding delay produced in a digital data receiver such as a decoder (Viterbi decoder) or deinterleaver of 8 or 16 vestigial sidebands (VSB) standard suggested as a DTV transmission system by the ATSC(Advanced Television Systems Committee).
2. Description of the Prior Art
FIG. 1 is a block construction view showing a forward error correction encoder of 8VSB standard suggested as the United States DTV transmission system by the ATSC. Here, in-data is received into a random numbering device 1 to be random and is encoded in a Reed-Solomon encoder 2. An output of Reed-Solomon encoder 2 is interleaved in an interleaver 3 for removing a burst error, and out-data is obtained by being subjected to a trellis encoding in a trellis encoder 4.
FIG. 2 is a block construction view showing the forward error correction decoder, in which input data in-data is decoded in a trellis decoder 5 to be deinterleaved in a deinterleaver 6. An output of deinterleaver 6 is decoded in a Reed-Solomon decoder 7, so that out-data to be random by random numbering device 1 is to be reversely random in a reverse-random numbering device 8 to be provided as the original data. Here, trellis decoder 5 is embodied by the Viterbi decoding algorithm which has an attribute for decoding by performing the back-tracing after receiving data of a prescribed quantity to have the decoding delay between the input and output of trellis decoder 5.
FIG. 3 illustrates the internal construction of deinterleaver 6, in which the output delay with respect to the input of deinterleaver 6 appears in proportion to the depth of interleaver 3.
FIG. 4 shows a data frame of the VSB standard by the ATSC, in which one segment consists of 832 symbols, and initial four symbols of each segment are a segment sync signal and 828 symbols are data. One field consists of data of 312 segments and a field sync signal of one segment, and one frame consists of two fields. Also, four symbols constitute one byte in 8VSB, and 2 symbols constitute one byte in 16VSB. Once the in-data stream having the above-stated format is received into trellis decoder 5 of the forward error correcting decoder shown in FIG. 2, the decoded data is provided from trellis decoder 5 after delaying by a prescribed period. The decoded data provided at this time involves a time differential as long as the sync signal of the input side and decoding delay time as shown in FIG. 5. The decoding delay may be indicated by a delay of one segment unit using the field sync as a reference and a delay of one byte unit using the segment sync as a reference. additionally, as shown in FIG. 5B, error data as long as the sync signal interval exists in the midst of the decoding output to incite the same problem in deinterleaver 6 as well as trellis decoder 5 except for the length of the delay time.
The time differential between the sync signal and decoding output can be solved by delaying the sync signal as long as the decoding delay time by using a flip-flop, but the use of the flip-flop incurs considerable cost in allotting the chip area and clock allocation when the decoding delay time is excessively long.
In case of the 8VSB standard by the ATSC, the trellis decoder delay is more than 250 clocks and deinterleaver delay is more than 10,000 clocks. For this reason, the delay of the sync signal by the flip-flop wastes the chip area and induces a serious problem in allotting clocks.
Furthermore, a memory may be utilized to economize the chip area, which, however, has a drawback of requiring a separate logic circuit for generating addresses of the memory.